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sm802149 156.25mhz/312.5mhz and 78.125mhz/156.25mhz lvds clock synthesizer clockworks? flex clockworks is a trademark of micrel, inc . micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com march 1, 2013 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 general description the sm802149 is a member of the clockworks ? family of devices from micrel and provides an extremely low - noise timing solution. it is based on a unique patented clockw orks flex architecture that provides very low phase noise. the device operates from a 3.3v or 2.5v power supply and synthesizes eight differential lvds clocks, four at 156.25mhz and four at 3125mhz , or four at 78 .125mhz and four at 156.25mhz. the sm8 02149 accepts a 26.04166mhz crystal or external lvcmos input. datasheets and support documentation are available on micrel?s web site at: www.micrel.com . features ? generates eight d ifferential lvds clocks : either f our at 156.25mhz and four at 312.5mhz , or f our at 78.125mhz and four at 156.25mhz ? 2.5v or 3.3v operating range ? typical phase jitter (1.875mhz to 20mhz): 99fs ? industrial temperature range ? green, rohs, and pfos compliant ? available in 44 - pin 7mm 7mm qfn packag e typical application
micrel, inc. sm802149 march 1, 2013 2 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 ordering information ( 1 ) part number marking shipping temperature range package sm802149umg 802149 tray ? 40c to +85c 44- pin qfn sm802149umg r 802149 tape and reel ? 40c to +85c 44- pin qfn note: 1. devices are green, rohs, and pfos compliant. pin configuration 44- pin qfn 7mmx7mm (top view)
micrel, inc. sm802149 march 1, 2013 3 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 pin description pin number pin name pin type pin level pin function 25, 26 28, 29 32, 33 35, 36 /q1, q1 /q2, q2 /q3, q3 /q4, q4 o, (dif) lvds differen tial clock outputs from bank 1 312.50mhz/156.25mhz 41, 42 1, 2 4, 5 7, 8 /q5, q5 /q6, q6 /q7, q7 /q8, q8 o, (dif) lvds differential clock outputs from bank 2 156.25mhz/ 78.125mhz 31, 37, 38 vddo1 pwr power supply for the outputs on bank 1 43, 44, 16 vddo2 pwr power supply for the outputs on bank 2 24, 39 vsso1 pwr power supply ground for the outputs on bank 1 3, 6, 40 vsso2 pwr power supply ground for the outputs on bank 2 23 gnd i, (se) this pin is n ot a power supply ground, but must be tied to vss 10 xtal_sel i, (se) lvcmos selects pll input reference source 0 = ref_in 1 = xtal 45k ? pull -up 11, 20, 27, 30, 34 test factory test pins. do not connect anything to these pins. 12, 13 vdd pwr core power supply 21 vss (exposed pad) pwr core power supply ground. the exposed pad must be connected to the vss ground plane. 9 pll_bypass i, (se) lvcmos pll bypass is a dual - function input. normal operation selects output source. 0 = normal pll o peration 1 = output from c rystal oscillator 45k ? pull - down 18 xtal_in i, (se) 10pf crystal crystal reference input. n o load caps needed. see figure 5 . 19 xtal_out o, (se) 10pf crystal crystal reference output. n o load caps needed. see figure 5 . 17 ref_in i, (se) lvcmos 26.04166mhz reference clock input 14 fsel i, (se) lvcmos frequency select. 1 = 312.5mhz/ 156.25 mhz 0 = 156.25mhz/78.125mhz. internal 45k pull - up 15 oe1 i, (se) lvcmos output enabl e. q1 q4 disables to tri - state. 0 = disabled 1 = enabled 45k pull - up 22 oe2 i, (se) lvcmos output enab le. q5 q8 disables to tri - state. 0 = disabled 1 = enabled 45k pull - up
micrel, inc. sm802149 march 1, 2013 4 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 truth tables pll_bypass xtal_sel oe1 oe2 input output 0 1 1 pll 1 1 1 xtal/ref_in 0 1 1 ref_in 1 1 1 xtal 0 1 q1 ? 4 tri -s tate 1 0 q5 ? 8 tri -s tate fsel output frequency (mhz) 0 156.25/78.125 1 312.50/156.25
micrel, inc. sm802149 march 1, 2013 5 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 absolute maximum ratings ( 2 ) supply voltage (v dd , v ddox ) ........................................ +4.6v input voltage (v in ) .................................. ? 0.5v to v dd +0.5v lead temperature (soldering, 20s) ............................ 260c case temperature ..................................................... 115 c storage temperature (ts) ......................... ? 65c to +150c operating ratings ( 3 ) supply voltage (v dd, v ddox ) ................. +2.375v to +3.465v ambient temperature (t a ) .......................... ? 40c to +85c junction thermal resistance (4) qfn ( ja ) still - air ......................................................... 24c/w qfn ( jb ) junction to board .......................................... 8c/w dc electrical characteristics ( 5 ) v dd = v ddo1/2 = 3.3v 5% or 2.5v 5%, v dd = 3.3v 5%, v ddo1/2 = 3.3v 5% or 2.5v 5%, t a = ? 40 c to + 85c. symbol parameter condition min. typ. max. units v dd, v ddo1/2 3.3v operating voltage v ddo1 = v ddo2 3.135 3.3 3.465 v 2.5v operating voltage v ddo1 = v ddo2 2.375 2.5 2.625 v outputs loaded 156.25mhz 181 235 ma outputs loaded 312.5mhz 216 280 lvcmos i nput ( oe1, oe2, pll_bypass) dc electrical characteristics ( 5 ) v dd = 3.3v 5%, or 2.5v 5%, t a = ? 40 c to + 85c. symbol parameter condition min. typ. max. units v ih input high voltage 2 v dd + 0.3 v v il input low voltage ? 0.3 0.8 v i ih input high current v dd = v in = 3.465v 150 a i il input low current v dd = 3.465v, v in = 0v ? 150 a ref_in dc electrical characteristics ( 5 ) v dd = 3.3v 5%, or 2.5v 5%, t a = ? 40 c to + 85c. symbol parameter condition min. typ. max. units v ih input high voltage 1.1 v dd + 0.3 v v il input low voltage ? 0.3 0.6 v i in input current v in = 0v to v dd ? 5 5 a notes: 2. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional opera tion is no t implied at conditions other than those detailed in the operational sections of this datasheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability . 3. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings . 4. package therm al resistance assumes exposed pad is soldered (or equivalent) to the device ? s most negative potential on the pcb . 5. the circuit is designed to meet the ac and dc specifications shown in the above table s after thermal equilibrium has been established .
micrel, inc. sm802149 march 1, 2013 6 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 cryst al characteristics parameter condition min. typ. max. units mode of oscillation 10pf l oad fundamental, parallel resonant frequency 26.04166 mhz equivalent series resistance (esr) 50 ? shunt capacitor, c0 1 5 pf correlation drive level 10 100 w lvds output dc electrical characteristics ( 5 ) v dd = v ddo1/2 = 3.3v 5% or 2.5v 5%, v dd = 3.3v 5%, v ddo1/2 = 3.3v 5% or 2.5v 5%, t a = 40 c to + 85 c. r l = 100 across q and /q. symbol parameter condition min . typ . max . units v od differential output voltage figure 1 , figure 4 275 350 475 mv v od v od magnitude change 40 mv v os offset voltage 1.15 1.25 1.50 v v os v os magnitude change 50 mv ac electrical characteristics ( 5 , 6 ) v dd = v ddo1/2 = 3.3v 5% or 2.5v 5%, v dd = 3.3v 5%, v ddox1/2 = 3.3v 5% or 2. 5v 5%, t a = 40 c to + 85 c. symbol parameter condition min . typ . max . units f out output frequency 1 fsel = 1, q1 q4 312.5 mhz output frequency 2 fsel = 1, q5 ? q8 156.2 5 mhz f out output frequency 1 fsel = 0, q1 ? q4 156.25 mhz output frequency 2 fsel = 0, q5 ? q8 78.125 mhz t r /t f output rise/fall time 20%? 80%, figure 2 , figure 4 100 220 400 ps t skew output -to - output skew within bank. note 7 45 ps odc output duty cycle lvds outputs 48 50 52 % t lock pll lock time 20 m s rms phase jitter ( 8 ) (output = 156.25mhz) integration r ange: 12khz ? 20mhz 260 fs integration r ange: 1.875mhz ? 20mhz 105 fs rms phase jitter ( 8 ) (output = 312.5mhz) inte gration r ange: 12khz ? 20mhz 250 fs integration r ange: 1.875mhz ? 20mhz 99 fs notes: 6. all phase noise measurements were taken with an agilent 5052b phase noise system. 7. defined as skew between outputs at the same supply voltage and with equal load conditions; measured at the output differentia l crossing points. 8. measured using a 26.04166 mhz crystal as the input reference source. if using an external reference inp ut, use a low phase noise source. with an external reference, the phase noise will follow the input source phase noise up to about 1mhz.
micrel, inc. sm802149 march 1, 2013 7 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 phase noise plots 156. 25mhz lvds integrated jitter 12k hz ? 20mhz = 262fs 156.25mhz lvds integrated jitter 1.875mhz ? 20mhz = 105fs
micrel, inc. sm802149 march 1, 2013 8 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 phase noise plots (continued) 312 .5mhz lvds integrated jitter 12khz ? 20mhz = 252fs 312 .5mhz lvds integrated jitter 1.875mhz ? 20mhz = 99 fs
micrel, inc. sm802149 march 1, 2013 9 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 application information input reference when operating w ith a crystal input reference, do not apply a switching signal to ref_in. crystal layout keep the layers under the crystal as open as possible and do not place switching signals or noisy supplies under the crystal. crystal load capacitance is built inside the die so no external capacitance is needed. see the selecting a quartz c rystal for the clockworks flex i family of precision synthesizers application note for further details. contact micrel?s hbw applications group if you need assistance to select a suitable crystal for your application at hbwhelp@micrel.com lvds outputs terminate lvds outputs with 100 across q and /q. for best performance , load all outputs. outputs can be dc or ac - coupled. figure 1 . duty cycle timing figure 2 . all outputs rise/fall time figure 3 . rms phase/noise/jitter
micrel, inc. sm802149 march 1, 2013 10 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 figure 4 . lvds output load figure 5 . crystal input interface
micrel, inc. sm802149 march 1, 2013 11 revision 1.1 hbwhelp@micrel.com or (408) 955 - 1690 package information ( 9 ) 44- pin 7mm 7mm qfn package note: 9. package information is correct as of the publication date. for updates and most current information, go to www.micrel.com . micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474- 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in th is data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provide d in micrel?s terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitn ess for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal func tion of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be r easonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages r esulting from such use or sale. ? 20 13 micrel, incorporated.

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